1. Technical Field
The present invention relates generally to communicating data between different voltage and frequency domains within an integrated circuit chip, and to mitigating propagation delays for data communication between domains.
2. Description of the Related Art
When designing electronics, power consumption is often a critical metric. Cell phones, handheld electronics, and other battery-powered electronic devices are measured in terms of battery life and play time. Even non-battery applications are striving to be as energy-friendly as possible. One way to promote efficient power consumption is by partitioning chips into multiple voltage and frequency domains. The voltages and frequencies in the different areas of the chip can be scaled to use minimum power while still achieving performance requirements. When data is communicated between different domains having different operating voltages and frequencies, the voltage and frequency are changed from that of the transmitting domain to that of the target domain.
Exchanging data across differently clocked domains can take place using synchronous or non-synchronous transfer. To guard against corrupting the data, synchronous transfer generally involves careful clock balancing across voltages and frequencies. In some cases, synchronous transfer implementations can use a negative edge to transfer the data, but the switching speeds provided by negative edge triggered flip-flops may not always be sufficient.
Non-synchronous data transfer across different voltage and frequency domains includes source-synchronous transfer and asynchronous transfer. Source-synchronous transfer involves sourcing a clock along with the data. Specifically, the timing of data signals transferred from one domain to another is referenced to the clock sourced by the transmitting domain, and not to a global clock. In source-synchronous transfer, any signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device. This comes at the expense of creating separate clock domains at the receiving domain, and thus additional synchronization logic to transfer the received data into the core clock of the receiving domain.
Asynchronous transmission of data occurs without the use of a dedicated clock signal. Any timing required to recover data from the communication symbols is encoded within the symbols. Asynchronous systems can be constructed out of modular functional blocks within an integrated circuit (IC), each module having well-defined communication interfaces. These modules may operate at variable speeds, whether due to data-dependent processing, dynamic voltage scaling, or process variation. The modules can then be combined together to form a working system, without reference to a global clock signal. Typically, low power is obtained since components are activated only on demand.
A specific type of IC is an application specific integrated circuit (ASIC). Such ASICs can provide flexibility to the system design. The ability to integrate millions of gates on an application specific integrated circuit (ASIC) has given rise to the System-on-Chip (SoC), or System-Level-Integration ASIC models. In such models, complex cores can be modularized into many smaller functional pieces. The functional pieces may include clusters of analog and digital logic, conventionally known and referred to herein as logic blocks, or synonymously, “chiplets.” A logic block or group of analog or digital circuits is sometimes called a chiplet. A chiplet (or logic block) may define a single module or a collection of modules having a particular physical hierarchy or boundary. Two or more chiplets can be on the same integrated circuit substrate or can be on different substrates. The logic blocks are connectable together in various configurations using data lines or other circuitry. The term “core” refers to each of the various functional blocks that make up an ASIC, and a chiplet can be thought of as a core, or functional block, of relatively low complexity, for example an application or system controller, a debug subsystem, an audio subsystem, an SoC interconnect, a memory, a clock generation unit, or the like. Functional blocks can range in size and complexity from a simple RAM memory core to a much more complex embedded processor core.